This invention relates to flash-type analog-to-digital (A/D) converters in general and more particularly to a decoder apparatus for error prevention in such converters.
As is well known, flash-type A/D converters also referred to as parallel converters or simultaneous A/D converters are widely employed to develop ultra-fast conversions which are of the type for example required in video signal processing, radar applications and other applications as well.
Such converters employ an analog comparator for every quantization level in the coded digital word. Since the conversion is performed in one step, rates of 100 megabits per second can be achieved. However, because the amount of equipment needed is practically doubled for each additional binary bit of resolution, parallel converters are usually employed with a requirement for low resolution that is a high speed 3-to-8 bit conversion system.
A limitation of the method in parallel converters is the large number of comparators required even for moderate resolution. Such large numbers of comparators have been provided in the prior art using CMOS technology with large scale integrated circuits. For example, a 4-bit converter requires only 15 comparators but an 8-bit converter needs 255 comparators. Hence the prior art has employed many techniques in order to improve operation of such parallel converters. For examples of typical devices, reference is made to a text entitled "Analog-To-Digital/Digital-To-Analog Conversion Techniques" by David F. Hoeschele, Jr., published by John Wiley & Sons, Inc. 1968 (See Chapter 12 entitled "Analog-To-Digital Converter Design", pages 366 to 429. There are of course many other examples of flash analog-to-digital converters in the prior art.
As is indicated, in the flash analog-to-digital converter whether it be fabricated from CMOS technology or otherwise certain errors can occur at specific sampling frequencies and input bandwidth. For example, in a high-speed CMOS 8-bit flash converter analog-to-digital measurement is made by comparing an input signal applied to 255 separate comparators each of which compare the input signal against 255 separate taps on a reference resistance ladder. The measurement point ideally can be logically decoded by establishing a tap where all comparisons below the tap are low (L), and ideally all above are high (H). This is approximated in a practical 256-to-8 decoding scheme based on testing all combinations of three adjacent comparators so that the selected tap is high and the taps immediately above and below it are high and low respectively (i.e. HHL sequence). It is also noted that more complicated sequences as for example HHLL can lead to non-correctable errors when a mistake is made. In this case, the sequence HHLHLL would not decode for an error one bit away from ideal. The HHL sequence always decodes and ensures that the error must be two bits away.
The basic problem has been that if the input signal is slewing rapidly, infrequent mistakes at isolated comparators can occur so that more than one measurement point will be decoded as the logical OR of the two measurements. Although such erroneous measurements occur near the true value, they can decode to non-serious errors or serious errors. A serious error would be a full scale output for near mid-point inputs. These are obviously unacceptable.
It is therefore an object of the present invention to provide a decoding method whereby serious ORing errors are rejected based on inhibiting an incorrect reading.
It is a further object to provide an improved decoder configuration for error prevention in a flash-type high-speed analog-to-digital converter.